M59DR032E-ZB datasheet(8/43 Pages) STMICROELECTRONICS

Part #	M59DR032E-ZB

Description	32 Mbit (2Mb x 16, Dual Bank, Page ) 1.8V Supply Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M59DR032EA, M59DR032EB

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SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

During a write operation the address inputs are

latched on the falling edge of Chip Enable E or

Write Enable W, whichever occurs last.

Data Input/Output (DQ0-DQ15). The Data I/O

output the data stored at the selected address dur-

ing a Bus Read operation or input a command or

the data to be programmed during a Write Bus op-

eration.

Both input data and commands are latched on the

rising edge of Write Enable W. The data output is

the Memory Array, the Common Flash Interface,

the Electronic Signature Manufacturer or Device

codes, the Block Protection status, the Configura-

tion Register status or the Status Register Data

depending on the address.

The data bus is high impedance when the chip is

deselected, Output Enable G is at VIH, or RP is at

VIL.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at VIH the device is deselected and the power con-

sumption is reduced to the standby level.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When Output Enable is at VIH the outputs

are high impedance.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Write Protect is at VIL, the

locked-down blocks cannot be locked or unlocked.

When Write Protect is at VIH, the Lock-Down is

disabled and the locked-down blocks can be

locked or unlocked. (refer to Table 10, Lock Sta-

tus).

Reset/Power-Down Input (RP). The Reset/Pow-

er-Down input provides hardware reset of the

memory, and/or Power-Down functions, depend-

ing on the Configuration Register status. A Reset

or Power-Down of the memory is achieved by pull-

ing RP to VIL for at least tPLPH.

The Reset/Power-Down function is set in the Con-

figuration Register (see Set Configuration Regis-

ter command). If it is set to ‘0’ the Reset function is

enabled, if it is set to ‘1’ the Power-Down function

is enabled. After a Reset or Power-Up the power

save function is disabled and all blocks are locked.

The memory Command Interface is reset on Pow-

er Up to Read Array. Either Chip Enable or Write

Enable must be tied to VIH during Power Up to al-

low maximum security and the possibility to write a

command on the first rising edge of Write Enable.

After a Reset, when the device is in Read, Erase

Suspend Read or Standby, valid data will be out-

put tPHQ7V1 after the rising edge of RP. If the de-

vice is in Erase or Program, the operation will be

aborted and the reset recovery will take a maxi-

mum of tPLQ7V. The memory will recover from

Power-Down tPHQ7V2 after the rising edge of RP.

See Tables 17, 18 and Figure 11.

VDD and VDDQ Supply Voltage (1.65V to 2.2V).

VDD provides the power supply to the internal core

of the memory device. It is the main power supply

for all operations (read, program and erase).

VDDQ provides the power supply to the I/O pins.

VDD and VDDQ must be at the same voltage.

VPP Programming Voltage (11.4V to 12.6V). VPP

provides a high voltage power supply for fast fac-

tory programming. VPP is required to use the Dou-

ble

Word

and

Quadruple

Word

Program

commands.

VSS Ground. VSS ground is the reference for the

core supply. It must be connected to the system

ground.

Note: Each device in a system should have

VDD, VDDQ and VPP decoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 6, AC Mea-

surement Load Circuit. The PCB trace widths

should be sufficient to carry the required VPP

program and erase currents.

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