3.5

Signal Handling

10

______________________________________________________________________________________

tR < 20ns

tF < 20ns

50%

LOGIC

INPUT

COM_

GND

IN_

(

)

0V

NO_

SWITCH

OUTPUT

LOGIC

INPUT

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

MAX4851_

MAX4853_

0V

SWITCH

INPUT

NORMAL MODE

NORMAL MODE

HIGH-Z MODE

Test Circuits/Timing Diagrams

Figure 1. Switching Time

90%

50%

10%

90%

50%

10%

INPUT A

INPUT A-

90%

50%

10%

90%

50%

10%

OUTPUT B

OUTPUT B-

B-

A-

A

B

TxD+

TxD-

Ω

Figure 2. Input/Output Skew Timing Diagram