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CY7C1009V33L-20VC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7C1009V33L-20VC
Description  128K x 8 Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1009V33L-20VC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7C1009V33
CY7C109V33
4
Switching Characteristics[4] Over the Operating Range
7C1009V33-12
7C109V33-12
7C1009V33-15
7C109V33-15
7C1009V33-20
7C109V33-20
7C1009V33-25
7C109V33-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
15
20
20
ns
tAA
Address to Data Valid
12
15
20
20
ns
tOHA
Data Hold from Address Change
3
33
3
ns
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
12
15
20
20
ns
tDOE
OE LOW to Data Valid
67
8
8
ns
tLZOE
OE LOW to Low Z
0
00
0
ns
tHZOE
OE HIGH to High Z[5, 6]
67
8
8
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[6]
3
33
3
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[5, 6]
67
8
8
ns
tPU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
0
00
0
ns
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
12
15
20
20
ns
WRITE CYCLE[7,8]
tWC
Write Cycle Time
12
15
20
20
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write
End
10
12
15
15
ns
tAW
Address Set-Up to Write End
10
12
15
15
ns
tHA
Address Hold from Write End
0
00
0
ns
tSA
Address Set-Up to Write Start
0
00
0
ns
tPWE
WE Pulse Width
10
12
15
15
ns
tSD
Data Set-Up to Write End
7
810
10
ns
tHD
Data Hold from Write End
0
00
0
ns
tLZWE
WE HIGH to Low Z[6]
3
33
3
ns
tHZWE
WE LOW to High Z[5, 6]
67
8
8
ns
Shaded areas contain preliminary information.
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
Description
Conditions
Min.
Max
Unit
VDR
VCC for Data Retention
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
V
ICCDR
Data Retention Current
200
µA
tCDR
Chip Deselect to Data Retention Time
0
ns
tR
Operation Recovery Time
tRC
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
8.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.


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