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74LVT574PWDH Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVT574PWDH Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 12 page Philips Semiconductors Product specification 74LVT574 3.3V Octal D-type flip-flop (3-State) 1998 Feb 19 3 LOGIC SYMBOL (IEEE/IEC) EN C1 1D SV00033 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 11 1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enable input (active-low) 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs 19, 18, 17, 16, 15, 14, 13, 12 Q0-Q7 Data outputs 11 CP Clock pulse input (active rising edge) 10 GND Ground (0V) 20 VCC Positive supply voltage FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING OE CP Dn REGISTER Q0 – Q7 MODE L L ↑ ↑ l h L H L H Load and read register L ↑ X NC NC Hold H X X NC Z Disable outputs H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition ↑ = not a Low-to-High clock transition LOGIC DIAGRAM 19 CP Q D 2 D0 Q0 CP Q D 3 D1 CP Q D 4 D2 CP Q D 5 D3 CP Q D 6 D4 CP Q D 7 D5 CP Q D 8 D6 CP Q D 9 D7 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 11 CP 1 OE SV00043 |
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