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MCP6232 Datasheet(PDF) 7 Page - Microchip Technology |
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MCP6232 Datasheet(HTML) 7 Page - Microchip Technology |
7 / 20 page 2004 Microchip Technology Inc. DS21881B-page 7 MCP6231/2 3.0 APPLICATION INFORMATION The MCP6231/2 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6231/2 ideal for battery-powered applications. 3.1 Rail-to-Rail Input The MCP6231/2 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 3-1 shows the input voltage exceeding the supply voltage without any phase reversal. FIGURE 3-1: The MCP6231/2 Show No Phase Reversal. The input stage of the MCP6231/2 op amps use two differential input stages in parallel. One operates at low common mode input voltage (VCM) and the other at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM =VSS – 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS – 0.3V to VDD + 0.3V at 25°C) can cause excessive current to flow into or out of the input pins. Current beyond ±2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 3-2. FIGURE 3-2: Input Current-Limiting Resistor (RIN). 3.2 Rail-to-Rail Output The output voltage range of the MCP6231/2 op amps is VDD –35mV (min.) and VSS + 35 mV (max.) when RL =10kΩ is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. 3.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 3-3) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. It does not, however, improve the bandwidth. FIGURE 3-3: Output resistor, RISO stabilizes large capacitive loads. Figure 3-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the gain are equal. For inverting gains, GN is 1 + |Gain| (e.g., –1 V/V gives GN = +2 V/V). -1 0 1 2 3 4 5 6 0.E+00 1.E+00 2.E+00 3.E+00 4.E+00 5.E+00 6.E+00 7.E+00 8.E+00 9.E+00 1.E+01 Time (1 ms/div) V DD = 5.0V G = +2 V/V V IN VOUT R IN V SS Minimum expected V IN () – 2 mA ---------------------------------------------------------------------------- ≥ R IN Maximum expected V IN () V DD – 2 mA ------------------------------------------------------------------------------- ≥ VIN RIN VOUT MCP623X – + VIN RISO VOUT MCP623X CL – + |
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