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83C575 Datasheet(PDF) 9 Page - NXP Semiconductors |
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83C575 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 40 page  Philips Semiconductors Product specification 80C575/83C575/ 87C575 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer 1998 May 01 9 POWER ON CLEAR/ POWER ON FLAG An on-chip Power On Detect Circuit resets the 8XC575 and sets the Power Off Flag (PCON.4) on power up or if VCC drops to zero momentarily. The POF can only be cleared by software. The RST pin is not driven by the power on detect circuit. The POF can be read by software to determine that a power failure has occurred and can also be set by software. LOW VOLTAGE DETECT An on-chip Low Voltage Detect circuit sets the Low Voltage Flag (PCON.3) if VCC drops below VLOW (see DC Electrical Characteristics) and resets the 8XC575 if the Low Voltage Reset Enable bit (WDCON.4) is set. If the LVRE is cleared, the reset is disabled but LVF will still be set if VCC is low. The RST pin is not driven by the low voltage detect circuit. The LVF can be read by software to determine that VCC was low. The LVF can be set or cleared by software. OSCILLATOR FAIL DETECT An on-chip Oscillator Fail Detect circuit sets the Oscillator Fail Flag (PCON.5) if the oscillator frequency drops below OSCF for one or more cycles (see AC Electrical Characteristics: OSCF) and resets the 8XC575 if the Oscillator Fail Reset Enable bit (WDCON.3) is set. If OFRE is cleared, the reset is disabled but OSF will still be set if the oscillator fails. The RST pin is not driven by the oscillator fail detect circuit. The OSF can be read by software to determine that an oscillator failure has occurred. The OSF can be set or cleared by software. LOW ACTIVE RESET One of the most notable features on this part is the low active reset. At this time this is the only 80C51 derivative available that has low active reset. This feature makes it easier to interface the 8XC575 into an application to accommodate the power-on and low voltage conditions that can occur. The low active reset operates exactly the same as high active reset with the exception that the part is put into the reset mode by applying a low level to the reset pin. For power-on reset it is also necessary to invert the power-on reset circuit; connecting the 8.2K resistor from the reset pin to VCC and the 10µf capacitor from the reset pin to ground. Figure 1 shows all of the reset related circuitry. When reset the port pins on the 87C575 are driven low asynchronously. This is different from all other 80C51 derivatives. The 8XC575 also has Low voltage detection circuitry that will, if enabled, force the part to reset when VCC (on the part) fails below a set level. Low Voltage Reset is enabled by a normal reset. Low Voltage Reset can be disabled by clearing LVRE (bit 4 in the WDCON SFR) then executing a watchdog feed sequence (A5H to WFEED1 followed immediately by 5A to WFEED2). In addition there is a flag (LVF) that is set if a low voltage condition is detected. The LVF flag is set even if the Low Voltage detection circuitry is disabled. Notice that the Low voltage detection circuitry does not drive the RST# pin so the LVF flag is the only way that the microcontroller can determine if it has been reset due to a low voltage condition. The 8XC575 has an on-chip power-on detection circuit that sets the POF (PCON.4) flag on power up or if the VCC level momentarily drops to 0V. This flag can be used to determine if the part is being started from a power-on (cold start) or if a reset has occurred due to another condition (warm start). TIMERS The 87C575 has four on-chip timers. Timers 0 and 1 are identical in every way to Timers 0 and 1 on the 80C51. Timer 2 on the 8XC575 is identical to the 80C52 Timer 2 (described in detail in the 80C52 overview) with the exception that it is an up or down counter. To configure the Timer to count down the DCEN bit in the T2MOD special function register must be set and a low level must be present on the T2EX pin (P1.1). The Watchdog timer operation and implementation is the same as that for the 8XC550 (described in the 8XC550 overview) with the exception that the reset values of the WDCON and WDL special function registers have been changed. The changes in these registers cause the watchdog timer to be enabled with a timeout of 98304 × TOSC when the part is reset. The watchdog can be disabled by executing a valid feed sequence and then clearing WDRUN (bit 2 in the WDCON SFR). PRE2 PRE1 PRE0 LVRE OFRE WDRUN WDTOF WDMOD WDCON (C0H) SHADOW REGISTER FOR WDCON WATCHDOG FEED SMOD1 SMOD0 OSF LVF GF0 GF1 IDL PCON (87GH) OSC FREQ BELOW OSCF (MIN FREQUENCY) RST + – VCC VLOW (LOW VCC REFERENCE) POWER-ON DETECT PCA WATCHDOG WATCHDOG TIMER 8xC575 INTERNAL RESET POF SU00239 Figure 1. Reset Circuitry |
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