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SC87C451CGA68 Datasheet(PDF) 11 Page - NXP Semiconductors |
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SC87C451CGA68 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 22 page  Philips Semiconductors Product specification 80C451/83C451/87C451 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O 1998 May 01 11 AC ELECTRICAL CHARACTERISTICS1 Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)2 12MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency: Speed Versions SC8XC451 C 3.5 12 MHz SC8XC451 G 3.5 16 MHz tLHLL 2 ALE pulse width 127 2tCLCL–40 ns tAVLL 2 Address valid to ALE low 28 tCLCL–55 ns tLLAX 2 Address hold after ALE low 48 tCLCL–35 ns tLLIV 2 ALE low to valid instruction in 234 4tCLCL–100 ns tLLPL 2 ALE low to PSEN low 43 tCLCL–40 ns tPLPH 2 PSEN pulse width 205 3tCLCL–45 ns tPLIV 2 PSEN low to valid instruction in 145 3tCLCL–105 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 59 tCLCL–25 ns tAVIV 2 Address to valid instruction in 312 5tCLCL–105 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tRLRH 3, 4 RD pulse width 400 6tCLCL–100 ns tWLWH 3, 4 WR pulse width 400 6tCLCL–100 ns tRLDV 3, 4 RD low to valid data in 252 5tCLCL–165 ns tRHDX 3, 4 Data hold after RD 0 0 ns tRHDZ 3, 4 Data float after RD 97 2tCLCL–70 ns tLLDV 3, 4 ALE low to valid data in 517 8tCLCL–150 ns tAVDV 3, 4 Address to valid data in 585 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 200 300 3tCLCL–50 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 203 4tCLCL–130 ns tQVWX 3, 4 Data valid to WR transition 23 tCLCL–60 ns tWHQX 3, 4 Data hold after WR 33 tCLCL–50 ns tRLAZ 3, 4 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 43 123 tCLCL–40 tCLCL+40 ns Shift Register tXLXL 5 Serial port clock cycle time 1.0 12tCLCL µs tQVXH 5 Output data setup to clock rising edge 700 10tCLCL–133 ns tXHQX 5 Output data hold after clock rising edge 50 2tCLCL–117 ns tXHDX 5 Input data hold after clock rising edge 0 0 ns tXHDV 5 Clock rising edge to input data valid 700 10tCLCL–133 ns NOTES: SEE NEXT PAGE |
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