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P80C528FBBB Datasheet(PDF) 9 Page - NXP Semiconductors |
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P80C528FBBB Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 26 page  Philips Semiconductors Product specification 80C528/83C528 CMOS single-chip 8-bit microcontrollers 1995 Feb 02 9 Table 2. Internal and External Program Memory Access with Security Bit Set INSTRUCTION ACCESS TO INTERNAL PROGRAM MEMORY ACCESS TO EXTERNAL PROGRAM MEMORY MOVC in internal program memory YES YES MOVC in external program memory NO YES ROM CODE PROTECTION By setting a mask programmable security bit, the ROM content in the 83C528 is protected, i.e., it cannot be read out by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is ‘don’t care’ after RESET (also if security bit is not set). This implementation prevents reading from internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to logical one. If the security bit has been set to a logical 0 there are no restrictions for the MOVC instructions. INTERNAL DATA MEMORY The internal data memory is divided into three physically separated segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes special function area. These can be addressed each in a different way. – RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. – RAM 128 to 255 can only be addressed indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. – AUX-RAM 0 to 255 is indirectly addressed in the same way as external data memory with the MOVX instructions. Address pointers are R0, R1 of the selected register bank and DPTR. An access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6 and P3.7. An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 8051 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that these external data memory cannot be accessed with R0 and R1 as address pointer. TIMER 2 Timer 2 is functionally equal to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter. These 16 bits are formed by two special function registers TL2 and TH2. Another pair of special function register RCAP2L and RCAP2H form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and 1, it can operate either as a timer or as an event counter. This is selected by bit C/T2N in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator mode which are selected by bits in T2CON. WATCHDOG TIMER T3 The watchdog timer consists of an 11-bit prescaler and an 8-bit timer formed by special function register T3. The prescaler is incremented by an on-chip oscillator with a fixed frequency of 1MHz. The maximum tolerance on this frequency is –50% and +100%. The 8-bit timer increments every 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset and a reset output pulse of 16 × 2048 cycles of the on-chip oscillator is generated at pin RST. The internal RESET signal is not inhibited when the external RST pin is kept low by, for example, an external reset circuit. The RESET signal drives port 1, 2, 3 into the high state and port 0 into the high impedance state. The watchdog timer is controlled by one special function register WDCON with the direct address location A5H. WDCON can be read and written by software. A value of A5H in WDCON halts the on-chip oscillator and clears both the prescaler and timer T3. After the RESET signal, WDCON contains A5H. Every value other than A5H in WDCON enables the watchdog timer. When the watchdog timer is enabled, it runs independently of the XTAL-clock. Timer T3 can be read on the fly. Timer T3 can only be written if WDCON contains the value 5AH. A successful write operation to T3 will clear the prescaler and WDCON, leaving the watchdog enabled and preventing inadvertent changes of T3. To prevent an overflow of the watchdog timer, the user program has to reload the watchdog timer within periods that are shorter than the programmed watchdog timer internal. This time interval is determined by an 8-bit value that has to be loaded in register T3 while at the same time the prescaler is cleared by hardware. Watchdog timer interval = [256 * (T3)] 2048 on * chip oscillator frequency BIT-LEVEL I2C INTERFACE This bit-level serial I/O interface supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C specification concerning the input levels and output drive capability. Consequently, these pins have an open drain output configuration. All the four modes of the I2C-bus are supported: – master transmitter – master receiver – slave transmitter – slave receiver The advantages of the bit-level I2C hardware compared with a full software I2C implementation are: – the hardware can generate the SCL pulse – Testing a single bit (RBF respectively, WBF) is sufficient as a check for error free transmission. The bit-level I2C hardware operates on serial bit level and performs the following functions: – filtering the incoming serial data and clock signals – recognizing the START condition – generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock – recognizing the STOP condition – recognizing a serial clock pulse on the SCL line – latching a serial bit on the SDA line (SDI) – stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit |
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