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S87C751-1N24 Datasheet(PDF) 10 Page - NXP Semiconductors |
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S87C751-1N24 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 24 page  Philips Semiconductors Product specification 83C751/87C751 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count 1998 May 01 10 Special Function Register – Interrupt Subsystem Because the interrupt structure is single level on the 83C751, there is no need for the IP SFR, so it is not used. Serial Communications The 8XC751 contains an I2C serial communications port instead of the 80C51 UART. The I2C serial port is a single bit hardware interface with all of the hardware necessary to support multimaster and slave operations. Also included are receiver digital filters and timer (timer I) for communication watch-dog purposes. The I2C serial port is controlled through four special function registers; I2C control, I2C data, I2C status, and I2C configuration. Special Function Register – Serial Communications The 83C751 contains many of the special function registers (SFR) that are found on the 80C51. Due to the different peripheral features on the 83C751, there are several additional SFRs and several that have been changed. Since the standard UART found on the 80C51 has been replaced by the I2C serial interface, the UART SFRs, SCON, and SBUF have been replaced by I2CON and I2DAT, and two additional I2C registers have been added (I2STA and I2CFG). I/O Port Latches (P0, P1, P3) The port latches function the same as those on the 80C51. Since there is no port 2 on the 83C751, the P2 latch is not used. Port 0 on the 83C751 has only 3 bits, so only 3 bits of the P0 SFR have a useful function. Special Function Register – I/O Port Latches There is no Port2 on the 8XC751, so P2 is not used. Also, only 3 bits of P0 SFR have a useful function. Data Pointer (DPTR) The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). In the 80C51 this register allows the access of external data memory using the MOVX instruction. Since the 83C751 does not support MOVX or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a MOVC instruction. DPTR may also be manipulated as two independent 8-bit registers. Table 2. I2C Special Function Register Addresses REGISTER ADDRESS BIT ADDRESS NAME SYMBOL ADDRESS MSB LSB I2C control I2CON 98 9F 9E 9D 9C 9B 9A 99 98 I2C data I2DAT 99 – – – – – – – – I2C configuration I2CFG D8 DF DE DD DC DB DA D9 D8 I2C status I2STA F8 FF FE FD FC FB FA F9 F8 ROM CODE SUBMISSION When submitting ROM code for the 80C751, the following must be specified: 1. 2k byte user ROM data ADDRESS CONTENT BIT(S) COMMENT 0000H to 07FFH DATA 7:0 User ROM Data |
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