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S80C552-AB Datasheet(PDF) 11 Page - NXP Semiconductors

Part # S80C552-AB
Description  Single-chip 8-bit microcontroller
Download  24 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

S80C552-AB Datasheet(HTML) 11 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13
11
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AIDD
Analog supply current: operating: (16MHz)
Port 5 = 0 to AVDD
1.2
mA
Analog supply current: operating: (24MHz, 30MHz)
Port 5 = 0 to AVDD
1.0
mA
AIID
Idle mode:
P83(0)C552EBx
50
µA
P83(0)C552EFx
50
µA
P83(0)C552EHx
100
µA
P83(0)C552IBx
50
µA
P83(0)C552IFx
50
µA
P83(0)C552KBx
50
µA
AIPD
Power-down mode:
2V < AVPD < AVDD max
P83(0)C552xBx
50
µA
P83(0)C552xFx
50
µA
P83(0)C552xHx
100
µA
AVIN
Analog input voltage
AVSS–0.2
AVDD+0.2
V
AVREF
Reference voltage:
AVREF–
AVSS–0.2
V
AVREF+
AVDD+0.2
V
RREF
Resistance between AVREF+ and AVREF–
10
50
k
CIA
Analog input capacitance
15
pF
tADS
Sampling time
8tCY
µs
tADC
Conversion time (including sampling time)
50tCY
µs
DLe
Differential non-linearity10, 11, 12
±1
LSB
ILe
Integral non-linearity10, 13
±2
LSB
OSe
Offset error10, 14
±2
LSB
Ge
Gain error10, 15
±0.4
%
Ae
Absolute voltage error10, 16
±3
LSB
MCTC
Channel to channel matching
±1
LSB
Ct
Crosstalk between inputs of port 517
0–100kHz
–60
dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;
EA = RST = STADC = XTAL1 = VSS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5V will be recognized as a logic
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: VDD – 0.2V < AVDD < VDD + 0.2V.
10. Conditions: AVREF– = 0V; AVDD = 5.0V, AVREF+ (80C552, 83C552) = 5.12V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AVIN = –20mV to 5.12V in steps of 0.5mV.
11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12. The ADC is monotonic; there are no missing codes.


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