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AD9380KSTZ-100 Datasheet(PDF) 10 Page - Analog Devices |
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AD9380KSTZ-100 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 60 page  AD9380 Rev. 0 | Page 10 of 60 Mnemonic Description EXTCLK/COAST External Clock. This allows the insertion of an external clock source rather than the internally generated PLL-locked clock. This pin is shared with the coast function, which does not affect EXTCLK functionality. PWRDN Power-Down Control/Three-State Control. The function of this pin is programmable via Register 0x26 [2:1]. FILT External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the PCB Layout Recommendations section . OUTPUTS HSOUT Horizontal Sync Output. A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and data, data timing with respect to horizontal sync can always be determined. VSOUT Vertical Sync Output. The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this output can be controlled via the serial bus bit (Register 0x24 [6]). SOGOUT Sync-on-Green Slicer Output. This pin outputs one of four possible signals (controlled by Register 0x1D [1:0]): raw SOG, raw HSYNC, regener- ated HSYNC from the filter, or the filtered HSYNC. See the Sync processing block diagram (see Figure 8 for pin connections). Note that besides slicing off SOG, the output from this pin is not processed on the AD9380. VSYNC separation is performed via the sync separator. O/E FIELD Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4]. SERIAL PORT SDA Serial Port Data I/O for Programming AD9380 Registers—I2C Address is 0x98. SCL Serial Port Data Clock for Programming AD9380 Registers. DDCSDA Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76. DDCSCL Serial Port Data Clock for HDCP Communications to Transmitter. Should be tied to 3.3 V through a 10 kΩ resistor. DATA OUTPUTS Red [7:0] Data Output, Red Channel. Green [7:0] Data Output, Green Channel. Blue [7:0] Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. DATA CLOCK OUTPUT DATACK Data Clock Output. This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained. |
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