Electronic Components Datasheet Search |
|
IDT72V36110L7.5BBI Datasheet(PDF) 7 Page - Integrated Device Technology |
|
IDT72V36110L7.5BBI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 48 page 7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 APRIL 6, 2006 NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 43-47 and Figures 31-33. PIN DESCRIPTION (PBGA PACKAGE ONLY) Symbol Name I/O Description ASYR(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW WritePort will select Asynchronous operation. TCK(2) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data Input seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data Output seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode I TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon power-up. If the JTAG function is not used then this signal should to be tied to GND. PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES) SEN Serial Enable I SENenablesserialloadingofprogrammableflagoffsets. WCLK/ WriteClock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK WR WriteStrobe writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, ( WEN should be tied to its active state). Asynchronous operation of the WCLK/WR input is only available in the PBGA package. WEN WriteEnable I WEN enables WCLK for writing data into the FIFO memory and offset registers. VCC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail. Symbol Name I/O Description NOTE: 1. Inputs should not change state after Master Reset. |
Similar Part No. - IDT72V36110L7.5BBI |
|
Similar Description - IDT72V36110L7.5BBI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |