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LC5512MC-75F484C Datasheet(PDF) 8 Page - Lattice Semiconductor

Part No. LC5512MC-75F484C
Description  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
8
Macrocell
The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks
and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP.
Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output
capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function
for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O
cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be
clocked from one of several global or product term clocks available on the device. A global and product term clock
enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset
for the macrocell register is provided from both global and product term signals. The macrocell register can be pro-
grammed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell.
Figure 8. Macrocell
Memory Modes
The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in
Table 4. The remainder of this section details operation of each of the memory modes. Additional information
regarding the memory modes can also be found in technical note number TN1030, Using Memory in ispXPLD
5000MX Devices.
PTSA Bypass
From
I/O Cell
Output to
I/O Block
GRP
PT Clock
From PTSA
PT Preset
PT Reset
Shared PT Reset
Shared
PT CE
CLK0
CLK1
Shared PT Clock
CLK2
CLK3
Global Reset
Clk En
Clk
R/L
D
PR
Q




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