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AMC1210IRHAT Datasheet(PDF) 6 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part # AMC1210IRHAT
Description  Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

AMC1210IRHAT Datasheet(HTML) 6 Page - Burr-Brown (TI)

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MODULATOR INPUT MODES
TIMING CHARACTERISTICS
Mode0
CLKx
INx
t
su1
t
h1
t
w1
t
w2
CLKx
INx
Mode1
t
su2
t
su2
t
h2
t
h2
t
w3
t
w4
Modulatorinternalclock
Modulatorinternaldata
Mode2
(Manchester-encodedbitstream)
1
0
1
1
0
0
1
1
1
t
w6
t
w5
INx
CLKx
INx
Mode3
(CLKxisdrivenexternally)
t
w7
t
w8
t
su3
t
h3
CLKx
INx
CLK
t
w11
Mode3
(CLKxisgeneratedbyAMC1210)
t
d11
t
w12
t
d2
t
w10
t
w9
t
su4
t
h4
AMC1210
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, CVDD = +5V, BVDD = +2.7V, unless otherwise
noted.
PARAMETER
MIN
MAX
UNIT
tw1
Mode 0 clock period CLKx
45
1/64th of CLK period
ns
tw2
Mode 0 clock high time CLKx
10
tw1 –10
ns
tsu1
Setup time from data valid to CLKx high
5
ns
th1
Hold time from CLKx high to data invalid
5
ns
tw3
Mode 1 clock period CLKx
90
1/128th of CLK period
ns
tw4
Mode 1 clock high time CLKx
20
tw3 –10
ns
tsu2
Setup time from data valid to CLKx high or low
5
ns
th2
Hold time from CLKx high or low to data invalid
5
ns
tw5
Mode 2 data width INx
45
ns
tw6
Mode 2 data pulse width INx
22
ns
tw7
Mode 3 clock period CLKx
22
1/32nd of CLK period
ns
tw8
Mode 3 clock high time CLKx
5
tw7 –5
ns
tsu3
Setup time from data valid to any CLKx high
5
ns
th3
Hold time from any CLKx high to data invalid
5
ns
tw9
System clock period CLK
11
ns
106
tw10
System clock high time CLK
3
tw9 –3
ns
tw11
Mode 3 generated clock period CLKx
tw9
tw9 x MD control bits
ns
tw12
Mode 3 generated high time CLKx
tw10 - 2
tw10 +2
ns
td1
Delay from system clock CLK high to generated CLKx high
0
3
ns
td2
Delay from system clock CLK low to generated CLKx low
0
3
ns
tsu4
Setup time from data valid to any CLKx high
5
ns
th4
Hold time from any CLKx high to data invalid
5
ns
Figure 1. Modulator Input Mode Timing
6
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