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ADF4156BCPZ Datasheet(PDF) 1 Page - Analog Devices |
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ADF4156BCPZ Datasheet(HTML) 1 Page - Analog Devices |
1 / 24 page 6 GHz Fractional-N Frequency Synthesizer ADF4156 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES RF bandwidth to 6 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/ ADF4153 and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADISimPLL Cycle slip reduction for faster lock times APPLICATIONS CATV equipment Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment GENERAL DESCRIPTION The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM LOCK DETECT N COUNTER CP RFCP3 RFCP2 RFCP4 RFCP1 REFERENCE DATA LE 32-BIT DATA REGISTER CLOCK REFIN AVDD AGND VDD VDD DGND RDIV SDOUT NDIV DGND CPGND DVDD VP CE RSET RFINA RFINB OUTPUT MUX MUXOUT – + HIGH Z PHASE FREQUENCY DETECTOR ADF4156 THIRD ORDER FRACTIONAL INTERPOLATOR MODULUS REG FRACTION REG INTEGER REG CURRENT SETTING ×2 DOUBLER 5-BIT R COUNTER CHARGE PUMP CSR /2 DIVIDER Figure 1. |
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