Applications Information

Output Termination

Terminate the outputs with 50

equivalent Thevenin terminations. Terminate OUT and

OUT with identical termination on each for low-output

distortion. When a single-ended signal is taken from the

differential output, terminate both OUT and OUT. Ensure

that output currents do not exceed the current limits as

specified in the Absolute Maximum Ratings. Under all

operating conditions, the device’s total thermal limits

should be observed.

Supply Bypassing

mount ceramic 0.1µF and 0.01µF capacitors. Place the

capacitors as close to the device as possible with the

0.01µF capacitor closest to the device pins.

Traces

Circuit board trace layout is very important to maintain

the signal integrity of high-speed differential signals.

Maintaining integrity is accomplished in part by reduc-

ing signal reflections and skew, and increasing com-

mon-mode noise immunity.

Signal reflections are caused by discontinuities in the

50

Ω characteristic impedance of the traces. Avoid dis-

continuities by maintaining the distance between differ-

ential traces, not using sharp corners or using vias.

Maintaining distance between the traces also increases

common-mode noise immunity. Reducing signal skew

is accomplished by matching the electrical length of

the differential traces.

Single LVDS/Anything-to-LVPECL Translator

_______________________________________________________________________________________

5

GND

Figure 1. Input Definitions

Chip Information

TRANSISTOR COUNT: 614

PROCESS: Bipolar

80%

OUT - OUT

20%

20%

80%

0V DIFFERENTIAL

0V DIFFERENTIAL

DIFFERENTIAL OUTPUT

WAVEFORM

IN

OUT

IN

OUT

Figure 2. Differential Input-to-Output Propagation Delay Timing

Diagram