ADS8413IRGZRG4 datasheet(6/38 Pages) BURR-BROWN

Part #	ADS8413IRGZRG4

Description	16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER

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Manufacturer	BURR-BROWN [Burr-Brown (TI)]

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ADS8413

SLAS490 – OCTOBER 2005

TIMING REQUIREMENTS (continued)

T

A = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

REF

Figure 7,

Figure 8,

td16

Delay time, CLK_O to SDO and SYNC_O 3-state

4

ns

Figure 12,

Figure 15

tpd1

Propagation delay time, SYNC_I to SYNC_O in daisy chain mode

11 + 0.5*tCLK

ns

Figure 12

td17

Delay time, SYNC_O and SDO 3-state to BUS_BUSY low in cascade mode.

0

2

ns

Figure 8

+VBD = 3.3 V

8

Delay time, RD rising edge to BUS_BUSY high for device with

Figure 11,

td18

ns

LAT_Y/N = 1

Figure 14

+VBD = 5 V

7

+VBD = 3.3 V

40.5

Delay time, point A indicating clear for bus 3-state release to BUSY

td19

ns

Figure 6

falling edge

+VBD = 5 V

40

tr

Rise time, differential LVDS output signal

950

ps

Figure 53

tf

Fall time, differential LVDS output signal

950

ps

Figure 53

CLK frequency (serial data rate)

190

210

MHz

Figure 22,

td20

Delay time, from PD falling edge to SDO 3-state

10

ns

Figure 23

Figure 22,

td21

Delay time, from PD falling edge to device powerdown

10

µs

Figure 23

Figure 22,

td22

Delay time, from PD rising edge to device powerup

25

ms

Figure 23

ts1

Settling time, internal reference after first three conversions

4

ms

Figure 22

td23

Delay time, CONVST falling edge to start of restricted zone for start of data read cycle

335

ns

Figure 9

td24

Delay time, CONVST falling edge to end of restricted zone for start of data read cycle

406

ns

Figure 9

6

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