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ADM6384 Datasheet(PDF) 9 Page - Analog Devices

Part # ADM6384
Description  Microprocessor Supervisory Circuit in 4-Lead SC70
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM6384 Datasheet(HTML) 9 Page - Analog Devices

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ADM6384
Rev. 0 | Page 9 of 12
CIRCUIT DESCRIPTION
VCC
1V
VCC
0V
VTH
VTH
0V
VCC
RESET
tRD
tRP
The ADM6384 provides microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal
when the supply voltage is below a preset threshold. In addition,
the ADM6384 allows supply voltage stabilization with a fixed
timeout before the reset deasserts after the supply voltage
rises above the threshold. If the user detects a problem with
the system’s operation, a manual reset input is available to reset
the microprocessor by means of an external push-button,
for example.
Figure 12. Reset Timing Diagram
MANUAL RESET INPUT
The ADM6384 features a manual reset input (MR) which, when
driven low, asserts the reset output. When MR transitions from
low to high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The
RESET OUTPUT
MR input has a
52 kΩ internal pull-up so that the input is always high when
unconnected. An external push-button switch can be connected
between
The ADM6384 features an active-low push-pull reset output.
The reset signal is guaranteed to be logic low for VCC down
to 1 V.
MR and ground so that the user can generate a reset.
Debounce circuitry for this purpose is integrated on-chip. Noise
immunity is provided on the
The reset output is asserted when VCC is below the reset
threshold (V
MR input, and fast, negative-going
transients of up to 100 ns (typ) are ignored. A 0.1 μF capacitor
between
TH
) or when MR is driven low. Reset remains
asserted for the duration of the reset active timeout period
(t
MR and ground provides additional noise immunity.
RP
) after VCC rises above the reset threshold or after MR
transitions from low to high. Figure 12 illustrates the behavior
of the reset outputs.


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