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SN65LVDS302ZQE Datasheet(PDF) 11 Page - Texas Instruments |
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SN65LVDS302ZQE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 41 page www.ti.com SN65LVDS302 SLLS733A – JUNE 2006 – REVISED AUGUST 2006 Table 4. Operating Mode Transitions MODE TRANSITION USE CASE TRANSITION SPECIFICS Shutdown → Standby Drive TXEN high to enable 1. RXEN high > 10 µs receiver 2. Receiver enters standby mode a. R[0:7]=G[0:7]=B[0:7]=VS=HS remain high and DE=PCLK low b. Receiver activates clock input monitor Standby → Acquire Receiver activity detected 1. CLK input monitor detects clock input activity 2. Outputs remain static 3. PLL circuit is enabled Acquire → Receive Link is ready to receive 1. PLL is active and approaches lock data 2. PLL achieves lock within twakeup 3. D1, D2, and/or D3 become active depending on LS0 and LS1 selection 4. First Data word was recovered 5. Parallel output bus turns on switching from static output pattern to output first valid data word Receive → Standby Transmitter requested to 1. Receiver disables outputs within tsleep enter Standby mode by 2. RX Input monitor detects VICM > 0.9 VDDLVDS within tsleep input common mode 3. R[0:7]=G[0:7]=B[0:7]=VS=HS transition to high and DE=PCLK to low on next voltage VICM > 0.9 VDDLVDS falling PLL clock edge (e.g. transmitter output clock stops or enters 4. PLL shuts down. Clock activity input monitor remains active high-impedance state) Receive/Standby → Turn off Receiver 1. RXEN pulled low for > tpwrdn Shutdown 2. Receiver switches all outputs into high-impedance state 3. Most IC circuitry is shut down for least power consumption 11 Submit Documentation Feedback |
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