 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SN65LVDS304 Datasheet(PDF) 6 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
SN65LVDS304 Datasheet(HTML) 6 Page - Texas Instruments |
|
|
6 / 38 page  www.ti.com SN65LVDS304 SLLS764 – SEPTEMBER 2006 TERMINAL FUNCTIONS NAME I/O DESCRIPTION D0+, D0– SubLVDS data link (active during normal operation) SubLVDS data link (active during normal operation when LS = high, high-impedance if LS = low); input D1+, D1– SubLVDS in can be left open if unused. CLK+, CLK– SubLVDS input pixel clock; polarity is fixed. R0–R7 Red-pixel data (8); pin assignment depends on SWAP pin setting. G0–G7 Green-pixel data (8); pin assignment depends on SWAP pin setting. B0–B7 Blue-pixel data (8); pin assignment depends on SWAP pin setting. HS CMOS out Horizontal sync VS Vertical sync DE Data enable PCLK Output pixel clock; rising or falling clock polarity is selected by control input CPOL. LS Link select (determines active SubLVDS data links and PLL range); see Table 2. Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode 1 – Receiver enabled 0 – Receiver disabled (shutdown) Note: The RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input RXEN must be pulled low for longer than 10 µs continuously to force the receiver to enter shutdown. The input must be pulled high for at least 10 µs continuously to activate the receiver. An input pulse shorter than 5 µs is interpreted as a glitch and becomes ignored. At power up, the receiver is enabled immediately if RXEN = H and disabled if RXEN = L. Output clock polarity selection CMOS In CPOL 0 – rising edge clocking 1 – falling edge clocking Bus swap swaps the bus pins to allow device placement on top or bottom of PCB. See pinout drawing for pin assignments. SWAP 0 – data output from R7...B0 1 – data output from B0...R7 CMOS bus rise time select F/S 1 – fast-output rise time 0 – slow-output rise time Channel parity error This output indicates the detection of a parity error by generating an output high-pulse for half of a PCLK clock cycle; this allows counting parity errors with a simple counter. CPE CMOS out 0 – no error high-pulse – bit error detected VDD Supply voltage GND Supply ground VDDLVDS SubLVDS I/O supply voltage GNDLVDS SubLVDS ground Power supply VDDPLLA PLL analog supply voltage GNDPLLA PLL analog GND VDDPLLD PLL digital supply voltage GNDPLLD PLL digital GND 6 Submit Documentation Feedback |
Similar Part No. - SN65LVDS304 |
|
Similar Description - SN65LVDS304 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
