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FUNCTIONAL DESCRIPTION

Deserialization Modes

1-Channel Mode

D0+/– CHANNEL

CLK+

B7 B6

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0

B5 B4 B3 B2 B1 B0 VS HS DE

CP R7 R6

T0161-01

CP

res

res

res

res

CLK–

2-Channel Mode

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP

res

B7 B6

G3 G2 G1 G0

B5 B4 B3 B2 B1 B0 HS DE res

CP

R7 R6

G3 G2

T0162-01

CLK+

CLK–

D0+/– Channel

D1+/– Channel

POWER-DOWN MODES

SHUTDOWN MODE

SN65LVDS304

SLLS764 – SEPTEMBER 2006

The SN65LVDS304 receiver has two modes of operation controlled by link-select pin LS. Table 2 shows the

deserializer modes of operation.

Table 2. Logic Table: Link Select Operating Modes

LS

Mode of Operation

Data Links Status

0

1ChM

1-channel mode (30-bit serialization rate)

D0 active

1

2ChM

2-channel mode (15-bit serialization rate)

D0, D1 active

While LS is held low, the SN65LVDS304 receives payload data over a single SubLVDS data pair, D0. The PLL

locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal high-speed

clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 3 illustrates the timing

and the mapping of the data payload into the 30-bit frame. The internal high-speed clock is divided by a factor of

30 to recreate the pixel clock, and the data payload with the pixel clock is presented on the output bus. The

reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the range of

4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the full

bandwidth capabilities of the SN65LVDS304.

Figure 3. Data and Clock Input in 1-ChM (LS = low)

While LS is held high, the SN65LVDS304 receives payload data over two SubLVDS data pairs, D0 and D1. The

PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15. The internal

high-speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data from each

pair. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal

high-speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel clock is

presented on the output bus. The reserved bits and parity bit are not output. While in this mode, the PLL can

lock to a clock that is in the range of 8 MHz through 30 MHz.

Figure 4. Data and Clock Output in 2-ChM (LS = high)

The SN65LVDS304 receiver has two power-down modes to facilitate efficient power management.

A low input signal on the RXEN pin puts the SN65LVDS304 into shutdown mode. This turns off most of the

receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The SubLVDS differential-input

resistance remains 100

Ω, and any input signal is ignored. All outputs hold a static output pattern:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.

7

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