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NZ48F000QTZ Datasheet(PDF) 11 Page - Intel Corporation |
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NZ48F000QTZ Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 106 page  Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 11 2.0 Functional Overview The Intel StrataFlash® Wireless Memory (L18) provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase, and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The Intel StrataFlash® Wireless Memory (L18) allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads do not cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the Intel StrataFlash® Wireless Memory (L18) incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the Intel StrataFlash® Wireless Memory (L18) supports read operations with VCC at 1.8 volt, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 volt, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the Intel StrataFlash® Wireless Memory (L18). An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments. The Intel StrataFlash® Wireless Memory (L18) offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The Intel StrataFlash® Wireless Memory (L18)’s protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zero-latency block locking and unlocking. |
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