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LM8333 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM8333 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 17 page 7.0 Device Operation (Continued) The data is sent from the slave to the host in the fourth byte. This byte ends with a negative acknowledgement (NACK) to indicate the end of the data. 7.6 WAKE-UP FROM HALT MODE Any bus transaction initiated by the host may encounter the LM8333 device in Halt mode or busy with processing data, such as controlling the FIFO buffer or executing interrupt service routines. Figure 10 shows the case in which the host sends a com- mand while the LM8333 is in Halt mode (CPU clock is stopped). Any activity on the ACCESS.bus wakes up the LM8333, but it cannot acknowledge the first bus cycle im- mediately after wake-up. The host drives a Start condition followed by seven address bits and a R/W bit. The host then releases SDA for one clock period, so that it can be driven by the LM8333. If the LM8333 does not drive SDA low during the high phase of the clock period immediately after the R/W bit, the bus cycle terminates without being acknowledged (shown as NACK in Figure 10). The host then aborts the transaction by sending a Stop condition. After aborting the bus cycle, the host may then retry the bus cycle. On the second attempt, the LM8333 will be able to acknowledge the slave address, because it will be in Active mode. Alternatively, the I 2C specification allows sending a START byte (00000001), which will not be acknowledged by any device. This byte can be used to wake up the LM8333 from Halt mode. The LM8333 may also stall the bus transaction by pulling the SCL low, which is a valid behavior defined by the I 2C specification. 20210611 FIGURE 9. Host Read Command 20210612 FIGURE 10. LM8333 Responds with NACK, Host Retries Command www.national.com 11 |
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