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IDT70T9359L7PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT70T9359L7PF Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 16 page 6.42 IDT70T9359/49L High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 2 Preliminary Description: The IDT70T9359/49 is a high-speed 8/4K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T9359/49 has been optimized forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An automatic power down feature, controlled by CE0and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 225mW of power. Index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100-Pin TQFP Top View(6) A9L A10L A11L A12L(1) NC NC NC LBL UBL CE0L CE1L CNTRSTL R/ WL OEL VDD FT/PIPEL I/O16L I/O17L I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 5640 drw 02 A8R A9R A10R A11R A12R(1) NC NC NC LBR UBR CE0R CNTRSTR R/ WR VSS OER FT/PIPER I/O14R I/O13R I/O12R I/O11R CE1R I/O17R VSS I/O16R I/O15R . 70T9359/49PF PN100-1(5) VSS 06/07/02 NOTES: 1. A12 is a NC for IDT70T9349. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. Pin Configurations (1,2,3,4) |
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