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IDT72T51256 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72T51256 Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 62 page 5 IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIALANDINDUSTRIAL TEMPERATURERANGES DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with up to 4 FIFO queues in parallel buffering between the two ports. The user can setup between 1 and 4 Queues within the device. Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths, independent of one another. MEMORY ORGANIZATION/ ALLOCATION The memory is organized into what is known as “blocks”, each block being 256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual queue sizes the user must allocate the memory to respective queues, in units of blocks, that is, a single queue can be made up from 0 to m blocks, where m is the total number of blocks available within a device. Also the total size of any given queue must be in increments of 256 x36. For the IDT72T51236/ 72T51246 and IDT72T51256 the Total Available Memory is 64, 128 and 256 blocks respectively (a block being 256 x36). Queues can be built from these blocks to make any size queue desired and any number of queues desired. BUS WIDTHS Theinputportiscommontoallqueueswithinthedevice,asistheoutputport. ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport and output port can be either x9, x18 or x36 bits wide provided that at least one of the ports is x36 bits wide, the read and write port widths being set independentlyofoneanother.Becausetheportsarecommontoallqueuesthe width of the queues is not individually set, so that the input width of all queues are equal and the output width of all queues are equal. WRITING TO & READING FROM THE MULTI-QUEUE Data being written into the device via the input port is directed to a discrete queue via the write queue select address inputs. Conversely, data being read fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame queue or different queues. Once a queue is selected for data writes or reads, the writing and reading operation is performed in the same manner as conventional IDT synchronous FIFO, utilizing clocks and enables, there is a single clock and enable per port. When a specific queue is addressed on the write port, data placed on the data inputs is written to that queue sequentially basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet. Conversely, data is read on to the output port after an access time from a rising edge on a read clock. Theoperationofthewriteportiscomparabletothefunctionofaconventional FIFO operating in standard IDT mode. Write operations can be performed on thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput provides status of the selected queue. The operation of the read port is comparable to the function of a conventional FIFO operating in FWFT mode. When a queue is selected on the output port, the next word in that queue will automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat queue require an enabled read cycle. Data cannot be read from a selected queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating when data read out is valid. If the user switches to a queue that is empty, the last word from the previous queue will remain on the output register. Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost full flag is similar to the almost full flag of a conventional IDT FIFO. The device provides a user programmable almost full flag for all 4 queues and when a respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus for that queue. Conversely, the read port has an output valid flag, providing status of the data being read from the queue selected on the read port. As well as the output valid flag the device provides a dedicated almost empty flag. This almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO. The device provides a user programmable almost empty flag for all 4 queues andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag provides status for that queue. PROGRAMMABLE FLAG BUSSES Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost full flag status bus is provided, this bus is 4 bits wide. Also, an almost empty flag status bus is provided, again this bus is 4 bits wide. The purpose of these flag busses is to provide the user with a means by which to monitor the data levels within queues that may not be selected on the write or read port. As mentioned, the device provides almost full and almost empty registers (programmable by the user) for each of the 4 queues in the device. The4bit PAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost Empty and Almost Full conditions of all 4 queue's. If the device is programmed for less than 4 queue's, then there will be a corresponding number of active outputs on the PAEn and PAFn busses. The flag busses can provide a continuous status of all queues. If devices are connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete form,providingconstantstatusofallqueues,orthebussesofindividualdevices can be connected together to produce a single bus of 4 bits. The device can then operate in a "Polled" or "Direct" mode. When operating in polled mode the flag bus provides status of each device sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow the status of each device in order. The rising edge of the write clock will update the Almost Full bus and a rising edge on the read clock will update the Almost Emptybus. When operating in direct mode the device driving the flag bus is selected by the user. The user addresses the device that will take control of a respective flag bus, these PAFn and PAEn flag busses operating independently of one another. Addressing of the Almost Full flag bus is done via the write port and addressing of the Almost Empty flag bus is done via the read port. PACKET MODE The multi-queue flow-control device also offers a “Packet Mode” operation. Packet Mode is user selectable and requires the device to be configured with both write and read ports as 36 bits wide. In packet mode, users can define the lengthofpacketsorframebyusingthetwomostsignificantbitsofthe36-bitword. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to mark the EndofPacket(EOP)asshowninTable5).Whenwritingdataintoagivenqueue , the first word being written is marked, by the user setting bit 34 as the “Start ofPacket”(SOP)andthelastwordwrittenismarkedasthe“EndofPacket”(EOP) withallwordswrittenbetweentheStartofPacket(SOP)marker(bit34)andthe End of packet (EOP) packet marker (bit 35) constituting the entire packet. A packet can be any length the user desires, up to the total available memory in the multi-queue device. The device monitors the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read port is supplied with an additional status flag, “Packet Ready”. The Packet Ready ( PR) flag in conjunction with OutputValid( OV)indicateswhenatleastonepacketisavailabletoread.When in packet mode the almost empty flag status , provides packet ready flag status for individual queues. |
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