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IDT70T9349L7BF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70T9349L7BF Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 16 page  ©2002 Integrated Device Technology, Inc. JULY 2002 DSC-5640/1 1 .unctional Block Diagram .eatures: x True Dual-Ported memory cells which allow simultaneous access of the same memory location x High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) x Low-power operation – IDT70T9359/49L Active: 225mW (typ.) Standby: 1.5mW (typ.) x Flow-Through or Pipelined output mode on either port via the FT/PIPE pins x Counter enable and reset features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode x Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility x LVTTL- compatible, single 2.5V (±100mV) power supply x Industrial temperature range (–40°C to +85°C) is available for 66MHz x Available in a 100-pin Thin Quad Flatpack (TQFP) and 100- pin fine pitch Ball Grid Array (fpBGA) packages. IDT70T9359/49L 0a 1a 0b 1b 0/1 ab I/O Control 1 0/1 0 FT/PIPER R/WR UBR LBR CE0R OER CE1R MEMORY ARRAY Counter/ Address Reg. 5640 drw 01 A12R(1) A0R CLKR ADSR CNTENR CNTRSTR I/O9L-I/O17L I/O0L-I/O8L I/O9R-I/O17R I/O0R-I/O8R A0L CLKL ADSL A12L(1) CNTENL CNTRSTL Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE1L 1 0/1 0 1b 0b 1a 0a 0/1 ba I/O Control FT/PIPEL HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY NOTE: 1. A12 is a NC for IDT70T9349. |
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