IDT72T51246L6BBI datasheet(8/62 Pages) IDT

Part #	IDT72T51246L6BBI

Description	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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Manufacturer	IDT [Integrated Device Technology]

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES

(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

PIN DESCRIPTIONS (CONTINUED)

FM(1)

Flag Mode

HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the

(K16)

INPUT

FM pin during Master Reset will determine whether the

PAFn and PAEn flag busses operate in either

Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.

FSTR

PAFn Flag Bus

LVTTL

If direct operation of the

PAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK

(R4)

Strobe

INPUT

and the WRADD bus to select a device for its queues to be placed on to the

PAFn bus outputs. A device

addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If

Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a

PAFn flag bus

selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted

and

SENO has gone LOW.

FSYNC

PAFn Bus Sync

LVTTL

FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the

PAFn bus

(R3)

OUTPUT

during Polled operation of the

PAFn bus. During Polled operation each device's queue status flags

are loaded on to the

PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads

device 1 onto

PAFn, the second WCLK rising edge loads device 2 and so on. During the WCLK cycle

that a selected device is placed on to the

PAFn bus, the FSYNC output will be HIGH.

FXI

PAFn Bus

LVTTL

The FXI input is used when multi-queue devices are connected in expansion mode and Polled

PAFn

(T2)

Expansion In

INPUT

bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI

receives a token from the previous device in a chain. In single device mode the FXI input must be tied

LOW if the

PAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput

must be connected to the FXO output of the same device. In expansion mode the FXI of the first device

should be tied LOW, when direct mode is selected.

FXO

PAFn Bus

LVTTL

FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled

(T3)

Expansion Out

OUTPUT

PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This

pin pulses when device N places its

PAE status on to the PAFn/PRn bus with respect to WCLK.

This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising

edge the first quadrant of device N+1 will be loaded on to the

PAFnbus.Thiscontinuesthroughthechain

and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device

in the chain provides synchronization to the user of this looping event.

ID[2:0](1)

Device ID Pins

HSTL-LVTTL For the 4Q multi-queue device the WRADD and RDADD address busses are 5 bits wide. When a queue

ID2-C9

INPUT

selection takes place the 3 MSb’s of this 5 bit address bus are used to address the specific device (the

ID1-A10

2 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s

ID0-B10

of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected

in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which

is ‘111’, however the ID does not have to match the device order. In single device mode these pins should

be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The

ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during

any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.

IOSEL

IO Select

LVTTL

This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are

(C8)

INPUT

required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.

IW(1)

InputWidth

LVTTL

ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination

(L15)

INPUT

of x9, x18 or x36, (providing that one port is x36).

MAST(1)

Master Device

HSTL-LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe

(K15)

INPUT

Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The

master device is the first to take control of all outputs after a master reset, all slave devices go to High-

Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this

pin must be set HIGH.

MRS

Master Reset

HSTL-LVTTL Amasterresetisperformedbytaking

MRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired

(T9)

INPUT

aftermasterreset.

NULL-Q

Null Queue

HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD

(J2)

Select

INPUT

and RADEN address bus to address the Null-Q.

Symbol &

Name

I/O TYPE

Description

Pin No.

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