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IDT71V428L15YYYGI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT71V428L15YYYGI Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 9 page 6.42 2 IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges Pin Configuration SOJ Top View Pin Description Truth Table(1,2) Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) A0 A1 A2 A3 A4 CS I/O 0 VDD VSS I/O 1 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A19 A18 A17 A16 A15 OE I/O 3 VSS VDD I/O 2 A14 A13 A12 A11 A10 NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SO32-3 3623 drw 02 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs ≥VHC or ≤VLC. A0 – A19 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input I/O0 - I/O3 Data Input/Output I/O VDD 3.3V Power Power VSS Ground Gnd 3623 tbl 02 Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 7 pF CI/O I/O Capacitance VOUT = 3dV 8 pF 3623 tbl 03 CS OE WE I/O Function LL H DATAOUT Read Data LX L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) VHC(3) X X High-Z Deselected - Standby (ISB1) 3623 tbl 01 |
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