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ADM1063ASU Datasheet(PDF) 3 Page - Analog Devices |
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ADM1063ASU Datasheet(HTML) 3 Page - Analog Devices |
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3 / 36 page  ADM1063 Rev. 0 | Page 3 of 36 GENERAL DESCRIPTION (continued from Page 1) Supply margining can be performed with a minimum of external components. The margining loop can be used for in-circuit testing of a board during production (for example, to verify the board’s functionality at −5% of nominal supplies), or it can be used dynamically to accurately control the output voltage of a dc-to-dc converter. The device also provides up to 10 programmable inputs for monitoring under, over, or out-of-window faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables. Six of these programmable outputs can provide up to a 12 V output for driving the gate of an N-channel FET, which can be placed in the path of a supply. Temperature measurement is possible with the ADM1063. The device contains one internal temperature sensor and two pairs of differential inputs for remote thermal diodes. These are measured by the 12-bit ADC. The logical core of the device is a sequencing engine. This state- machine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs. The device is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by ADI. GPI SIGNAL CONDITIONING SFD GPI SIGNAL CONDITIONING SFD SFD SFD SELECTABLE ATTENUATOR SELECTABLE ATTENUATOR DEVICE CONTROLLER OSC EEPROM SDA SCL A1 A0 SMBus INTERFACE REFOUT REFIN REFGND VREF 12-BIT SAR ADC ADM1063 CONFIGURABLE O/P DRIVER (HV) PDO1 PDO2 PDOGND PDO3 VCCP GND PDO4 PDO5 PDO8 PDO9 CONFIGURABLE O/P DRIVER (HV) PDO6 CONFIGURABLE O/P DRIVER (LV) PDO7 CONFIGURABLE O/P DRIVER (LV) PDO10 SEQUENCING ENGINE VX2 VX3 VX4 VP2 VP3 VP4 VH VP1 VX1 AGND VX5 VDDCAP VDD ARBITRATOR REG 5.25V CHARGE PUMP D2N D1N D2P D1P TEMP SENSOR INTERNAL DIODE Figure 2. Detailed Block Diagram |
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