7
UCC3957 -1/-2/-3/-4
1
2
3
4
5
6
7
10
9
8
16
15
14
13
12
11
DVDD
VDD
CLCNT
WU
AN1
AN2
AN3
AN4
BATLO
CHGEN
AN4
CHG
DCHG
CDLY2
AVDD
CDLY1
R1 1MEG
R2
10K
Q2
IRF7416
Q1
IFR7416
Q3
227002
VR1 18V
C4
0.022
µF
C1
0.1
µF
C2
0.1
µF
R
SENSE
.025
Ω
LI-ION BATTERY STACK
PACK (–)
PACK (+)
"CHARGE"
"DISCHARGE"
D1
1A, 50V
R3
1K
C5
0.22
µF
R4
100
C6
.22
µF
Figure 5. Four cell protector with slew rate limiting the discharge FET.
Note 1: VR1 and R2 are optional. They protect Q1 from excessive open-circuit charger voltage.
Note 2. R3 and C5 are chosen based on capacitive load that must be driven.
Note 3. R4 minimizes inductive kick at turn-off.
APPLICATION INFORMATION (continued)
UDG-98018
IC or the Discharge FET (Q2). For this reason, it is
strongly recommended that a capacitor (C5 in Fig’s 1 &
2) be placed across the cell stack, from VDD to AN4, and
that stray inductance be minimized in the battery current
path. An alternative to adding a capacitor across the cell
stack is to reduce the di/dt. This is discussed in the next
section.
Controlling Discharge FET Turn-on / Turn-off Times
By slew rate limiting the pack output voltage at turn-on,
the surge current into large capacitive loads can be
greatly reduced.
This allows the designer to select shorter overcurrent de-
lay times, minimizing the stress on Q1 and Q2 in the
event of a shorted pack output. A simple method of im-
plementing slew rate limiting is shown in Figure 5. It con-
sists of an RC network (R3 and C5) between gate and
drain of the Discharge FET (Q2) to control its turn-on
time. This circuit relies on the relatively high sink imped-
ance (about 20K) of the UCC3957’s DCHG output. The
values shown for R3 and C5 will provide a pack output
voltage rise time of about 4.5msec when the Discharge
FET (Q2) is turned on. Note that the addition of R3 and
C5 has made it possible to eliminate the CDLY2 capaci-
tor, for the quickest response to a true short circuit. While
this circuit will not prevent a large surge current when in-
serting a “live” battery pack into a highly capacitive load,
it will allow it to restart (after one hiccup cycle) if this ini-
tial surge current trips the overcurrent protection.
Increasing the turn-off time of the Discharge FET (Q2)
reduces the inductive kick that results during turn-off af-
ter an overcurrent condition. This is accomplished by
adding a resistor (R4) in series with the DCHG output.
This reduction of di/dt at turn-off will minimize (or elimi-
nate) the need for a capacitor across the battery stack. It
is recommended that this resistor value not exceed a few
hundred ohms, or the ability to turn off quickly enough
into a short may be compromised.
Due to the relatively low charge currents (typically a few
amps max), controlling the turn-on and turn-off times of
the Charge FET is not beneficial. In fact, the turn-off time
of the Charge FET will be slow due to the large value of
R1, the gate-source resistor.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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