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EVAL-ADF7021DB Datasheet(PDF) 10 Page - Analog Devices |
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EVAL-ADF7021DB Datasheet(HTML) 10 Page - Analog Devices |
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10 / 44 page  ADF7021 Preliminary Technical Data Rev. PrI | Page 10 of 44 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 35 34 33 32 31 30 29 28 27 26 25 ADF7021 TOP VIEW (Not to Scale) VCOIN CREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET CREG4 GND4 CLKOUT DATA CLK | TxDATA DATA I/O | RxDATA SWD VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE 1 2 3 4 5 6 7 8 9 10 11 12 PIN 1 INDICATOR Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. 2 CREG1 Regulator Voltage for PA Block. A 100 nF in parallel should be placed between this pin and ground for regulator stability and noise rejection. 3 VDD1 Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 100 pF should be placed as close as possible to this pin. All VDD pins should be tied together. 4 RFOUT The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. 5 RFGND Ground for Output Stage of Transmitter. All GND pins should be tied together. 6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. 7 RFINB Complementary LNA Input. See the LNA/PA Matching section. 8 RLNA External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. 9 VDD4 Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. 10 RSET External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ with 5% tolerance. 11 CREG4 Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. 12 GND4 Ground for LNA/MIXER Block. 13 to 18 MIX_I, MIX_I, MIX_Q, MIX_Q, FILT_I, FILT_I, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 19, 22 GND4 Ground for LNA/MIXER Block. 20, 21, 23 FILT_Q, FILT_Q, TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 24 CE Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. 25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. 26 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin. |
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