and 4 Open-Drain I/Os

_______________________________________________________________________________________

9

PIN

CONNECTION

DEVICE ADDRESS

OUTPUTS POWER-UP DEFAULT

AD2

AD0

A6

A5

A4

A3

A2

A1

A0

O15

O14

O13

O12

O11

O10

O9

O8

SCL

GND

10

100

00

11

11

00

00

SCL

V+

10

100

01

11

11

11

11

SCL

SCL

10

100

10

11

11

11

11

SCL

SDA

10

100

11

11

11

11

11

SDA

GND

10

101

00

11

11

00

00

SDA

V+

10

101

01

11

11

11

11

SDA

SCL

10

101

10

11

11

11

11

SDA

SDA

10

101

11

11

11

11

11

GND

GND

10

110

00

00

00

00

00

GND

V+

10

110

01

00

00

11

11

GND

SCL

10

110

10

00

00

11

11

GND

SDA

10

110

11

00

00

11

11

V+

GND

10

111

00

11

11

00

00

V+

V+

1

0

111

0

1

11

11

1

11

1

V+

SCL

10

111

10

11

11

11

11

V+

SDA

10

111

11

11

11

11

11

Table 3. MAX7327 Address Map for Outputs O8–O15

I/O Port Inputs

I/O port inputs switch at CMOS logic levels as deter-

mined by the expander’s supply voltage, and are over-

voltage tolerant to +6V, independent of the expander’s

supply voltage.

I/O Port Input Transition Detection

All I/O ports configured as inputs are monitored for

changes since the expander was last accessed

through the serial interface. The state of the ports is

stored in an internal “snapshot” register for transition

monitoring. The snapshot is continuously compared

with the actual input conditions, and if a change is

detected for any port input, INT is asserted to signal a

state change. The input ports are sampled (internally

latched into the snapshot register) and the old transi-

MAX7327 read and write access. The previous port

transition flags are read through the serial interface as

the second byte of a 2-byte read sequence.

A long read sequence (more than 2 bytes) can be used

to poll the expander continuously without the overhead

of resending the slave address. If more than 2 bytes

are read from the expander, the expander repeatedly

returns the 2 bytes of input port data followed by the

transition flags. The inputs are repeatedly resampled

and the transition flags repeatedly reset for each pair of

bytes read. All changes that occur during a long read

sequence are detected and reported.

The INT output is not reasserted during a read

sequence to avoid recursive reentry into an interrupt

service routine. Instead, if a data change occurs that

would normally cause the INT output to be set, the INT

assertion is delayed until the STOP condition. INT is not

reasserted upon a STOP condition if the changed input

data is read before the STOP occurs. The INT logic

ensures that unnecessary interrupts are not asserted,

yet data changes are detected and reported no matter

when the change occurs.