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HT82A822R Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT82A822R Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 41 page  HT82A822R Rev. 1.00 10 July 21, 2006 Oscillator Configuration There is an oscillator circuit in the microcontroller. This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an exter- nal signal to conserve power. A crystal across OSCI and OSCO is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSCI and OSCO to get a frequency reference, but two external capacitors in OSCI and OSCO are required. The WDT oscillator is a free running on-chip RC oscilla- tor, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or a instruction clock (sys- tem clock/4). The timer is designed to prevent a soft- ware malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. When the WDT clock source is selected, it will be first di- vided by 256 (8-stage) to get the nominal time-out pe- riod. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is typical 65 ms. This time-out pe- riod may vary with temperature, VDD and process varia- tions. The WDT OSC always works for any operation mode. If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the halt mode. In the mode, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RESET), software instruc- tion, and a ²HALT² instruction. There are two types of software instructions; ²CLR WDT² and the other set ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one type of instruction can be active at a time depending on the options ²CLR WDT² times selec- tion option. If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² in- struction clears the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. C r y s t a l O s c i l l a t o r O S C O O S C I System Oscillator S y s t e m C l o c k / 4 8 - b i t C o u n t e r W D T P r e s c a l e r 7 - b i t C o u n t e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 M a s k O p t i o n S e l e c t W D T O S C Watchdog Timer Bit No. Label Function 0 1 2 WS0 WS1 WS2 Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, division ratio = 1:1 Bit 2,1,0 = 001, division ratio = 1:2 Bit 2,1,0 = 010, division ratio = 1:4 Bit 2,1,0 = 011, division ratio = 1:8 Bit 2,1,0 = 100, division ratio = 1:16 Bit 2,1,0 = 101, division ratio = 1:32 Bit 2,1,0 = 110, division ratio = 1:64 Bit 2,1,0 = 111, division ratio = 1:128 3 ¾ Unused bit, read as ²0² 7~4 T3~T0 Test mode setting bits (T3, T2, T1, T0)=(0, 1, 0, 1), enter DAC write mode. Otherwise normal operation. WDTS (09H) Register |
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