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MCF5484 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

Part # MCF5484
Description  Microprocessor Electrical Characteristics
Download  28 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCF5484 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

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DC Electrical Specifications
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4
Freescale Semiconductor
3
3
DC Electrical Specifications
Table 4 lists DC electrical operating temperatures. This table is based on an operating voltage of
EVDD = 3.3 VDC ± 0.3 VDC and IVDD of 1.5 ± 0.07 VDC.
NOTES:
1
θ
JA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of
θ
JA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the
Ψ
jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2
Per JEDEC JESD51-6 with the board horizontal.
3
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
5
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
Table 4. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Units
External (I/O pads) operation voltage range
EVDD
3.0
3.6
V
Memory (I/O pads) operation voltage range (DDR Memory)
SD VDD
2.30
2.70
V
Internal logic operation voltage range 1
NOTES:
1
IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure 1 for an
example circuit. Note: There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input.
IVDD
1.43
1.58
V
PLL Analog operation voltage range 1
PLL VDD
1.43
1.58
V
USB oscillator operation voltage range
USB_OSVDD
3.0
3.6
V
USB digital logic operation voltage range
USBVDD
3.0
3.6
V
USB PHY operation voltage range
USB_PHYVDD
3.0
3.6
V
USB oscillator analog operation voltage range
USB_OSCAVDD
1.43
1.58
V
USB PLL operation voltage range
USB_PLLVDD
1.43
1.58
V
Input high voltage SSTL 3.3V (SDR DRAM)
VIH
2.0
3.6
V
Input low voltage SSTL 3.3V (SDR DRAM)
VIL
–0.5
0.8
V
Input high voltage SSTL 2.5V (DDR DRAM)
VIH
2.0
2.8
V
Input low voltage SSTL 2.5V (DDR DRAM)
VIL
–0.5
0.8
V
Output high voltage IOH = 8 mA, 16 mA,24 mA
VOH
2.4
V
Output low voltage IOL = 8 mA, 16 mA,24 mA
5
VOL
—0.5
V
Capacitance 2, Vin =0 V, f = 1 MHz
2
Capacitance CIN is periodically sampled rather than 100% tested.
CIN
—TBD
pF


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