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MPC8347 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPC8347 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 108 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 7 Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal charaistics for the MPC8347EA. The MPC8347EA is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.32 V PLL supply voltage AVDD –0.3 to 1.32 V DDR and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75 –0.3 to 1.98 V Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63 V PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD –0.3 to 3.63 V Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5 DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5 Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5 Local bus, DUART, CLKIN, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3, 5 PCI OVIN –0.3 to (OVDD + 0.3) V 6 Storage temperature range TSTG –55 to 150 •C Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. |
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