Micrel, Inc.

SY87700AL

November 2006

3

M9999-111406-B

Pin Description

Inputs

Pin Number

(28-SOIC)

Pin Number

(32-TQFP)

Pin Name

Pin Name

4,

5

2,

3

RDINP,

RDINN

Serial Data Input. Differential PECL: These built-in line receiver inputs are

connected to the differential receive serial data stream. An internal receive

PLL recovers the embedded clock (RCLK) and data (RDOUT) information.

The incoming data rate can be within one of eight frequency ranges

depending on the state of the FREQSEL pins. See “Frequency Selection”

Table.

7

5

REFCLK

Reference Clock. TTL Input: This input is used as the reference for the

internal frequency synthesizer and the “training” frequency for the receiver

PLL to keep it centered in the absence of data coming in on the RDIN inputs

27

26

CD

Carrier Detect. PECL Input: This input controls the recovery function of the

Receive PLL and can be driven by the carrier detect output of optical

modules or from external transition detection circuitry. When this input is

HIGH the input data stream (RDIN) is recovered normally by the Receive

PLL. When this input is LOW the data on the inputs RDIN will be internally

forced to a constant LOW, the data outputs RDOUT will remain LOW, the

Link Fault Indicator output LFIN forced LOW and the clock recovery PLL

forced to lock onto the clock frequency generated from REFCLK.

6

8

9

4

6

7

FREQSEL1

FREQSEL2

FREQSEL3

Frequency Select. TTL Inputs: These inputs select the output clock frequency

range as shown in the “Frequency Selection” Table.

3

26

32

25

DIVSEL1

DIVSEL2

Divider Select. TTL Inputs: These inputs select the ratio between the output

clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in

the “Reference Frequency Selection” Table.

17

16

CLKSEL

Clock Select. TTL Input: This input is used to select either the recovered

clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency

synthesizer (CLKSEL = LOW) to the TCLK outputs.

Outputs

2

31

LFIN

Link Fault Indicator. TTL Output: This output indicates the status of the input

data stream RDIN. Active HIGH signal is indicating when the internal clock

recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if

CD is HIGH and RDIN is within the frequency range of the Receive PLL

(1000ppm). LFIN is an asynchronous output.

25

24

24

23

RDOUTP

RDOUTN

Receive Data Output. Differential PECL: These ECL 100k outputs represent

the recovered data from the input data stream (RDIN). This recovered data is

specified against the rising edge of RCLK.

22, 21

21, 20

RCLKP,

RCLKN

Clock Output. Differential PECL: These ECL 100k outputs represent the

recovered clock used to sample the recovered data (RDOUT).

19, 18

18, 17

TCLKP,

TCLKN

Clock Output. Differential PECL: These ECL 100k outputs represent either

the recovered clock (CLKSEL = HIGH) used to sample the recovered data

(RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL =

LOW).

11, 12

9, 10

PLLSP,

PLLSN

Clock Synthesis PLL Loop Filter: External loop filter pins for the clock

synthesis PLL.

16, 15

15, 14

PLLRP,

PLLRN

Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.