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PREMILINARY
CY7C1302CV25
Document #: 38-05491 Rev. *A
Page 8 of 18
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
tHC
tHC
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)
0.7
0.8
1.0
ns
tHD
tHD
D[17:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
2.5
3.0
3.0
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
1.2
1.2
1.2
ns
tCHZ
tCHZ
Clock (CandC) RisetoHigh-Z(ActivetoHigh-Z)[19,20]
2.5
3.0
3.0
ns
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[19, 20]
1.2
1.2
1.2
ns
Notes:
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
Switching Characteristics Over the Operating Range (continued)[17]
Cypress
Parameter
Consortium
Parameter
Description
-167
-133
-100
Unit
Min. Max. Min. Max. Min. Max.
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