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THS1230CPW Datasheet(PDF) 11 Page - Texas Instruments |
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THS1230CPW Datasheet(HTML) 11 Page - Texas Instruments |
11 / 22 page www.ti.com −140 −120 −100 −80 −60 −40 −20 0 f − Frequency − MHz AVDD = DVDD = 3.3 V, fs = 30 MSPS, fi = 3.58 MHz, −1 dBFS, Mode 1 Differential −140 −120 −100 −80 −60 −40 −20 0 AVDD = DVDD = 3.3 V, fs = 30 MSPS, fi = 3.58 MHz, −1 dBFS, Mode 2 Differential f − Frequency − MHz PRINCIPLES OF OPERATION Analog Input THS1230 SLAS291B – OCTOBER 2000 – REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) FAST FOURIER TRANSFORM - MODE 1 Figure 12. FAST FOURIER TRANSFORM - MODE 2 Figure 13. The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC CORE, where the process of analog to digital conversion is performed against ADC reference voltages, VREFT and VREFB. Connecting the EXTREF pin to one of two voltages, DGND or DVDD selects one of the two configurations of ADC reference generation. The ADC reference voltages come from either the internal reference buffer or completely external sources. Connect EXTREF to DGND for internal reference generation or to DVDD for external reference generation. CON0 and CON1 as described below, select the input configuration mode or place the device in powerdown. The ADC core drives out through output buffers to the data pins D0 to D11. The output buffers can be disabled by the OE pin. A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on the rising edge of CLK, and corresponding data is output after the fifth following rising edge. The THS1230 can operate in differential Mode 1 or differential Mode 2, controlled by the configuration pins CON0 and CON1 as shown in Table 1. Mode 0 places the device in power-down state or standby for reduced power consumption. 11 |
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