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IDT70T15L20BFI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70T15L20BFI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 18 page  1 ©2002 Integrated Device Technology, Inc. AUGUST 2002 DSC 5663/1 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A13L(1) A0L 5663 drw 01 I/O0L-I/O8L CEL OEL R/ WL SEML INTL M/ S BUSYR A13R(1) A0R SEMR INTR CER OER (3) (2,3) (3) R/ WR CER OER R/ WR 14 14 I/O0R-I/O8R (2,3) .unctional Block Diagram x M/ S = VIH for BUSY output flag on Master M/ S = VIL for BUSY input on Slave x Busy and Interrupt Flag x On-chip port arbitration logic x Full on-chip hardware support of semaphore signaling between ports x Fully asynchronous operation from either port x LVTTL-compatible, single 2.5V (±100mV) power supply x Available in an 80-pin TQFP and 100-pin fpBGA x Industrial temperature range (–40°C to +85°C) is available for selected speeds .eatures x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x High-speed access – Commercial:20/25ns (max.) – Industrial: 25ns (max.) x Low-power operation – IDT70T16/5L Active: 200mW (typ.) Standby: 600 µW (typ.) x IDT70T16/5 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM IDT70T16/5L NOTES: 1. A13 is a NC for IDT70T15. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. PRELIMINARY |
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