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AT26DF081A-SSU Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT26DF081A-SSU Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 36 page  11 3600A–DFLASH–11/05 AT26DF081A [Preliminary] Figure 8-3. Sequential Program Mode – Status Register Polling Figure 8-4. Sequential Program Mode – Waiting Maximum Byte Program Time 8.3 Block Erase A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper- ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Reg- ister to a logical “1” state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the device will erase the appropriate block. The erasing of the block is internally self- timed and should take place in a time of t BLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. CS SI SO Opcode A23-16 A15-8 A7-0 05h Data HIGH-IMPEDANCE Opcode Data 05h 04h Opcode Data 05h STATUS REGISTER DATA STATUS REGISTER DATA STATUS REGISTER DATA Seqeuntial Program Mode Command First Address to Program Status Register Read Command Write Disable Command Seqeuntial Program Mode Command Seqeuntial Program Mode Command Note: Each transition shown for SI represents one byte (8 bits) CS SI SO Opcode A23-16 A15-8 A7-0 Data HIGH-IMPEDANCE Opcode Data 04h Opcode Data Seqeuntial Program Mode Command First Address to Program Write Disable Command Seqeuntial Program Mode Command Seqeuntial Program Mode Command Note: Each transition shown for SI represents one byte (8 bits) tBP tBP tBP |
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