 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT89S8253-24AU Datasheet(PDF) 10 Page - ATMEL Corporation |
|
||||||||||||||||||||||||||||||
AT89S8253-24AU Datasheet(HTML) 10 Page - ATMEL Corporation |
|
|
10 / 59 page  10 3286H–MICRO–9/05 AT89S8253 In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the byte being written with the MSB complemented. Once the write cycle is completed, true data are valid at all bit locations. 6.1 Memory Control Register The EECON register contains control bits for the 2K bytes of on-chip data EEPROM. It also con- tains the control bit for the dual data pointer. Figure 6-1. Data EEPROM Write Sequence Table 6-1. EECON – Data EEPROM Control Register EECON Address = 96H Reset Value = XX00 0011B Not Bit Addressable Bit – – EELD EEMWE EEMEN DPS RDY/BSY WRTINH 76543 2 1 0 Symbol Function EELD EEPROM data memory load enable bit. Used to implement Page Mode Write. A MOVX instruction writing into the data EEPROM will not initiate the programming cycle if this bit is set, rather it will just load data into the volatile data buffer of the data EEPROM memory. Before the last MOVX, reset this bit and the data EEPROM will program all the bytes previously loaded on the same page of the address given by the last MOVX instruction. EEMWE EEPROM data memory write enable bit. Set this bit to 1 before initiating byte write to on-chip EEPROM with the MOVX instruction. User software should set this bit to 0 after EEPROM write is completed. EEMEN Internal EEPROM access enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM instead of external data memory if the address used is less than 2K. When EEMEN = 0 or the address used is ≥ 2K, MOVX with DPTR accesses external data memory. DPS Data pointer register select. DPS = 0 selects the first bank of data pointer register, DP0, and DPS = 1 selects the second bank, DP1. RDY/BSY RDY/BSY (Ready/Busy) flag for the data EEPROM memory. This is a read-only bit which is cleared by hardware during the programming cycle of the on-chip EEPROM. It is also set by hardware when the programming is completed. Note that RDY/BSY will be cleared long after the completion of the MOVX instruction which has initiated the programming cycle. WRTINH WRTINH (Write Inhibit) is a READ-ONLY bit which is cleared by hardware when Vcc is too low for the programming cycle of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a new programming cycle will not start. 01 2 330 31 EEMWE EEMEN EELD MOVX DATA RDY/BSY 4 ms ~ |
Similar Part No. - AT89S8253-24AU |
|
Similar Description - AT89S8253-24AU |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
