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EPM7512B Datasheet(PDF) 2 Page - Altera Corporation |
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EPM7512B Datasheet(HTML) 2 Page - Altera Corporation |
2 / 66 page 2 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet ...and More Features ■ System-level features –MultiVoltTM I/O interface enabling device core to run at 2.5 V, while I/O pins are compatible with 3.3-V, 2.5-V, and 1.8-V logic levels – Programmable power-saving mode for 50% or greater power reduction in each macrocell – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Support for advanced I/O standards, including SSTL-2 and SSTL-3, and GTL+ – Bus-hold option on I/O pins –PCI compatible – Bus-friendly architecture including programmable slew-rate control – Open-drain output option – Programmable security bit for protection of proprietary designs – Built-in boundary-scan test circuitry compliant with IEEE Std. 1149.1 – Supports hot-socketing operation – Programmable ground pins ■ Advanced architecture features – Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance – Configurable expander product-term distribution, allowing up to 32 product terms per macrocell – Programmable macrocell registers with individual clear, preset, clock, and clock enable controls – Two global clock signals with optional inversion – Programmable power-up states for macrocell registers – 6 to 10 pin- or logic-driven output enable signals ■ Advanced package options – Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-saving FineLine BGATM, 0.8-mm Ultra FineLine BGA, and plastic J-lead chip carrier (PLCC) packages – Pin-compatibility with other MAX 7000B devices in the same package ■ Advanced software support – Software design support and automatic place-and-route provided by Altera’s MAX+PLUS® II development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations |
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