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IDT7035S20PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7035S20PF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 19 page ©1999 Integrated Device Technology, Inc. SEPTEMBER 1999 DSC 4088/5 1 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL BUSYL A12L A0L 4088 drw 01 UBL LBL CEL OEL I/O9L-I/O17L I/O0L-I/O8L CEL OEL R/WL SEML INTL M/S R/WR BUSYR UBR LBR CER OER I/O9R-I/O17R I/O0R-I/O8R A12R A0R R/WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 13 13 IDT7035S/L HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM Features x x x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x x x x x High-speed access Commercial: 15/20ns (max.) x x x x x Low-power operation IDT7035S Active: 800mW (typ.) Standby: 5mW (typ.) IDT7035L Active: 800mW (typ.) Standby: 1mW (typ.) x x x x x Separate upper-byte and lower-byte control for multiplexed bus compatibility x x x x x IDT7035 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device x x x x x M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave x x x x x Interrupt Flag x x x x x On-chip port arbitration logic x x x x x Full on-chip hardware support of semaphore signaling between ports x x x x x Fully asynchronous operation from either port x x x x x Battery backup operation2V data retention x x x x x TTL-compatible, single 5V (±10%) power supply x x x x x Available in 100-pin Thin Quad Flatpack Industrial temperature range (40°C to +85°C) is available for selected speeds Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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