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MB90F867APFV Datasheet(PDF) 4 Page - Fujitsu Component Limited. |
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MB90F867APFV Datasheet(HTML) 4 Page - Fujitsu Component Limited. |
4 / 62 page MB90860A Series 4 s PRODUCT LINEUP (Continued) Part Number Parameter MB90F867A (S) , MB90867A (S) MB90V340(S) CPU F2MC-16LX CPU System clock On-chip PLL clock multiplier ( ×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6) ROM Boot-block,Flash memory 128 Kbytes External RAM 6 Kbytes 30 Kbytes Emulator-specific power supply*1 Yes Technology 0.35 µm CMOS with on-chip voltage regulator for internal power supply + Flash memory with On-chip charge pump for programming voltage 0.35 µm CMOS with on-chip voltage regulator for internal power supply Operating voltage range 3.5 V to 5.5 V : at normal operating (not using A/D converter) 4.0 V to 5.5 V : at using A/D converter/Flash programming 4.5 V to 5.5 V : at using external bus 5 V ± 10% Temperature range −40 °C to +105 °C Package QFP-100, LQFP-100 PGA-299 UART 4 channels 5 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device I2C (400 Kbit/s) 2 channel A/D Converter 24 input channels 10-bit or 8-bit resolution Conversion time : Min 3 µs include sample time (per one channel) 16-bit Reload Timer (4 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function 16-bit I/O Timer (2 channels) Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 0, 4) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 16-bit Output Compare (8 channels (16-bit) / 16 channels (8-bit) ) Signals an interrupt when 16-bit I/O Timer match output compare registers. A pair of compare registers can be used to generate an output signal. 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Signals an interrupt upon external event |
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