PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Document #: 38-05353 Rev. *A
Page 8 of 27
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1464AV33 , BWa,b,c,d for CY7C1460AV33 and BWa,b for
CY7C1462AV33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max
Unit
IDDZZ
Sleep mode standby current
ZZ
> V
DD − 0.2V
100
mA
tZZS
Device operation to ZZ
ZZ
> V
DD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ
< 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Tri-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Tri-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Tri-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Tri-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Tri-State
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Tri-State
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
