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ADL5391ACPZ-R2 Datasheet(PDF) 10 Page - Analog Devices |
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ADL5391ACPZ-R2 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page ADL5391 Rev. 0 | Page 10 of 16 GENERAL DESCRIPTION BASIC THEORY The multiplication of two analog variables is a fundamental signal processing function that has been around for decades. By convention, the desired transfer function is given by W = αXY/U + Z (1) where: X and Y are the multiplicands. U is the multiplier scaling factor. α is the multiplier gain. W is the product output. Z is a summing input. All the variables and the scaling factor have the dimension of volts. In the past, analog multipliers, such as the AD835, were implemented almost exclusively with a Gilbert Cell topology or a close derivative. The inherently asymmetric signal paths for X and Y inevitably create amplitude and delay imbalances between X and Y. In the ADL5391, the novel multiplier core provides absolute symmetry between X and Y, minimizing scaling and phasing differences inherent in the Gilbert Cell. The simplified block diagram of the ADL5391 shows a main multiplier cell that receives inputs X and Y and a second multiplier cell in the feedback path around an integrating buffer. The inputs to this feedback multiplier are the difference of the output signal and the summing input, W − Z, and the internal scaling reference, U. At dc, the integrating buffer ensures that the output of both multipliers is exactly 0, therefore (W − Z)xU = XY, or W = XY/U + Z (2) By using a feedback multiplier that is identical to the main multiplier, the scaling is traced back solely to U, which is an accurate reference generated on-chip. As is apparent in Equation 2, noise, drift, or distortion that is common to both multipliers is rejected to first-order because the feedback multiplier essentially compensates the impairments generated in the main multiplier. The scaling factor, U, is fixed by design to 1.12 V. However, the multiplier gain, α, can be adjusted by driving the GADJ pin with a voltage ranging from 0 V to 2 V. If left floating, then α = 1 or 0 dB, and the overall scaling is simply U = 1 V. For VGADJ = 0 V, the gain is lowered by approximately 4 dB; for VGADJ = 2 V, the gain is raised by approximately 6 dB. Figure 5 shows the relationship between α(V/V) and VGADJ. The small-signal bandwidth from the inputs X, Y, and Z to the output W is a single-pole response. The pole is inversely proportional to α. For α = 1 (GADJ floating), the bandwidth is about 2 GHz; for α > 1, the bandwidth is reduced; and for α < 1, the bandwidth is increased. All input ports, X, Y, and Z, are differential and internally biased to midsupply, VPOS/2. The differential input impedance is 500 Ω up to 100 MHz, rolling off to 50 Ω at 2 GHz. All inputs can be driven in single-ended fashion and can be ac-coupled. In dc-coupled operation, the inputs can be biased to a common mode that is lower than VPOS/2. The bias current flowing out of the input pins to accommodate the lower common mode is subtracted from the 50 mA total available from the internal reference VPOS/2 at the VREF pin. Each input pin presents an equivalent 250 Ω dc resistance to VPOS/2. If all six input pins sit 1 V below VPOS/2, a total of 6 × 1 V/250 Ω = 24 mA must flow internally from VREF to the input pins. Calibration The dc offset of the ADL5391 is approximately 20 mV but changes over temperature and has variation from part to part (see Figure 4). It is generally not of concern unless the ADL5391 is operated down to dc (close to the point X = 0 V or Y = 0 V), where 0 V is expected on the output (W = 0 V). For example, when the ADL5391 is used as a VGA and a large amount of attenuation is needed, the maximum attenuation is determined by the input dc offset. Applying the proper voltage on the Z input removes the W offset. Calibration can be accomplished by making the appropriate cross plots and adjusting the Z input to remove the offset. Additionally, gain scaling can be adjusted by applying a dc voltage to the GADJ pin, as shown in Figure 5. BASIC CONNECTIONS Multiplier Connections The best ADL5391 performance is achieved when the X, Y, and Z inputs and W output are driven differentially; however, they can be driven single-ended. Single-ended-to-differential transformations (or differential-to-single-ended transformations) can be done using a balun or active components, such as the AD8313, the AD8132 (both with operation down to dc), or the AD8352 (for higher drive capability). If using the ADL5391 single-ended without ac coupling capacitors, the reference voltage of 2.5 V needs to be taken into account. Voltages above 2.5 V are positive voltages and voltages below 2.5 V are negative voltages. Care needs to be taken not to load the ADL5391 too heavily, the maximum reference current available is 50 mA. |
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