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IDT70T9159L Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70T9159L Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 16 page ©2002 Integrated Device Technology, Inc. JULY 2002 DSC-5654/1 1 .unctional Block Diagram .eatures x True Dual-Ported memory cells which allow simultaneous access of the same memory location x High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) x Low-power operation – IDT70T9169/59L Active: 225mW (typ.) Standby: 1.5mW (typ.) x Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins x Counter enable and reset features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode x LVTTL- compatible, single 2.5V (±100mV) power supply x Industrial temperature range (–40°C to +85°C) is available for 66MHz x Available in a 100-pin Thin Quad Flatpack (TQFP) and 100- pin fine pitch Ball Grid Array (fpBGA) packages. HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70T9169/59L 0 1 0/1 1 0/1 0 R/ WR OER CE0R CE1R FT/PIPER I/O Control MEMORY ARRAY Counter/ Address Reg. I/O Control 5654 drw 01 A13R(1) A0R CLKR ADSR CNTENR CNTRSTR A0L CLKL ADSL A13L(1) CNTENL CNTRSTL Counter/ Address Reg. R/WL CE0L OEL CE1L I/O0L -I/O8L I/O0R -I/O8R 1 0/1 0 0 1 0/1 FT/PIPEL PRELIMINARY NOTE: 1. A13 is a NC for IDT70T9159. |
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