SRAM
MT5C6405
Austin Semiconductor, Inc.
MT5C6405
Rev. 2.0 5/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS (GND).
2.
-3V for pulse width < 20ns
3.
I
CC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
tRC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as
in Fig. 2. Transition is measured ±200mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform
is inverted.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
123
123
123
123
1234
1234
1234
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
12345678
12345678
12345678
12345678
123
123
123
123
1234
1234
1234
1234
123456789
123456789
123456789
123456789
123
123
123
123
1234
1234
1234
1234
DATA RETENTION MODE
V
DR > 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
DESCRIPTION
SYM
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
---
V
Data Retention Current
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V
ICCDR
1mA
Chip Deselect to Data
Retention Time
tCDR
0
---
ns
4
Operation Recovery Time
tR
tRC
ns
4, 11
CONDITIONS
+5V
Q
255
30pF
480
5 pF
+5V
Q
255
480