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HY29F400ABG-70 Datasheet(PDF) 3 Page - Hynix Semiconductor |
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HY29F400ABG-70 Datasheet(HTML) 3 Page - Hynix Semiconductor |
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3 / 40 page  3 Rev. 1.0/Jan. 02 HY29F400A PIN CONFIGURATIONS Standard TSOP48 DQ7 DQ14 44 43 DQ6 DQ13 42 41 DQ5 DQ12 40 39 DQ4 V CC 38 37 DQ11 DQ3 36 35 DQ10 DQ2 34 33 DQ9 DQ1 32 31 DQ8 DQ0 30 29 A16 BYTE# 48 47 V SS DQ15/A-1 46 45 OE# V SS 28 27 CE# A0 26 25 A11 A10 5 6 A9 A8 7 8 NC NC 9 10 WE# RESET# 11 12 NC NC 13 14 RY/BY# NC 15 16 A17 A7 17 18 A6 A5 19 20 A15 A14 1 2 A13 A12 3 4 A4 A3 21 22 A2 A1 23 24 Reverse TSOP48 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 48 47 46 45 28 27 26 25 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 21 22 23 24 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A15 A14 A13 A12 A4 A3 A2 A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 A16 BYTE# V SS DQ15/A-1 OE# V SS CE# A0 A6 A5 5 6 A4 A3 7 8 A2 A1 9 10 A0 CE# 11 12 V SS OE# 13 14 DQ0 DQ8 15 16 DQ1 DQ9 17 18 DQ2 DQ10 19 20 DQ3 DQ11 21 22 NC RY/BY# 1 2 A17 A7 3 4 A10 A11 40 39 A12 A13 38 37 A14 A15 36 35 A16 BYTE# 34 33 V SS DQ15/A-1 32 31 DQ7 DQ14 30 29 DQ6 DQ13 28 27 DQ5 DQ12 26 25 DQ4 V CC 24 23 RESET# WE# 44 43 A8 A9 42 41 CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A ‘#’ symbol following the signal name, e.g., RESET#, indicates that the sig- nal is asserted in a Low state (nominally 0 volts). Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0]. The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadeci- mal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1). |
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