HY62UF16800B

Rev.02/Apr. 2002

5

TIMING DIAGRAM

READ CYCLE 1(Note 1,4)

READ CYCLE 2(Note 1,2,4)

tRC

tAA

Data Valid

Previous Data

tOH

tOH

ADDR

Data

Out

READ CYCLE 3(Note 1,2,4)

/CS1

/UB, /LB

tACS

Data Valid

tCLZ(3)

tCHZ(3)

Data

Out

CS2

Notes:

1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and

CS2 are in active status.

3. Transition is measured + 200mV from steady state voltage.

This parameter is sampled and not 100% tested.

4. /CS1 in high for the standby, low for active

CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active

Data Valid

High-Z

ADDR

Data

Out

tRC

/CS1

CS2

/UB ,/ LB

/OE

tAA

tACS

tBA

tOE

tOH